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| Features * High-performance, Low-power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture - 133 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers + Peripheral Control Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz - On-chip 2-cycle Multiplier Non volatile Program and Data Memories - 32K/64K/128K Bytes of In-System Reprogrammable Flash (AT90CAN32/64/128) * Endurance: 10,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits * Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes * In-System Programming by On-Chip Boot Program (CAN, UART, ...) * True Read-While-Write Operation - 1K/2K/4K Bytes EEPROM (Endurance: 100,000 Write/Erase Cycles) (AT90CAN32/64/128) - 2K/4K/4K Bytes Internal SRAM (AT90CAN32/64/128) - Up to 64K Bytes Optional External Memory Space - Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Programming Flash (Hardware ISP), EEPROM, Lock & Fuse Bits - Extensive On-chip Debug Support CAN Controller 2.0A & 2.0B - ISO 16845 Certified (1) - 15 Full Message Objects with Separate Identifier Tags and Masks - Transmit, Receive, Automatic Reply and Frame Buffer Receive Modes - 1Mbits/s Maximum Transfer Rate at 8 MHz - Time stamping, TTC & Listening Mode (Spying or Autobaud) Peripheral Features - Programmable Watchdog Timer with On-chip Oscillator - 8-bit Synchronous Timer/Counter-0 * 10-bit Prescaler * External Event Counter * Output Compare or 8-bit PWM Output - 8-bit Asynchronous Timer/Counter-2 * 10-bit Prescaler * External Event Counter * Output Compare or 8-Bit PWM Output * 32Khz Oscillator for RTC Operation - Dual 16-bit Synchronous Timer/Counters-1 & 3 * 10-bit Prescaler * Input Capture with Noise Canceler * External Event Counter * 3-Output Compare or 16-Bit PWM Output * Output Compare Modulation - 8-channel, 10-bit SAR ADC * 8 Single-ended Channels * 7 Differential Channels * 2 Differential Channels With Programmable Gain at 1x, 10x, or 200x - On-chip Analog Comparator - Byte-oriented Two-wire Serial Interface - Dual Programmable Serial USART - Master/Slave SPI Serial Interface * Programming Flash (Hardware ISP) Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - 8 External Interrupt Sources - 5 Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down & Standby - Software Selectable Clock Frequency - Global Pull-up Disable I/O and Packages - 53 Programmable I/O Lines - 64-lead TQFP and 64-lead QFN Operating Voltages: 2.7 - 5.5V Operating temperature: Industrial (-40C to +85C) Maximum Frequency: 8 MHz at 2.7V, 16 MHz at 4.5V 1. Details on section 19.4.3 on page 242. * * * * 8-bit Microcontroller with 32K/64K/128K Bytes of ISP Flash and CAN Controller AT90CAN32 AT90CAN64 AT90CAN128 Summary * * * * * Note: Rev. 7679HS-CAN-08/08 1. Description 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128 AT90CAN32, AT90CAN64 and AT90CAN128 are hardware and software compatible. They differ only in memory sizes as shown in Table 1-1. Table 1-1. Device AT90CAN32 AT90CAN64 AT90CAN128 Memory Size Summary Flash 32K Bytes 64K Bytes 128K Bytes EEPROM 1K Byte 2K Bytes 4K Byte RAM 2K Bytes 4K Bytes 4K Bytes 1.2 Part Description The AT90CAN32/64/128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90CAN32/64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT90CAN32/64/128 provides the following features: 32K/64K/128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1K/2K/4K bytes EEPROM, 2K/4K/4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a CAN controller, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differential input stage with programmable gain, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel's high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By 2 AT90CAN32/64/128 7679HS-CAN-08/08 AT90CAN32/64/128 combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90CAN32/64/128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 1.3 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 3 7679HS-CAN-08/08 1.4 Block Diagram Block Diagram Figure 1-1. PF7 - PF0 PA7 - PA0 PC7 - PC0 VCC GND PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC AGND AREF JTAG TAP PROGRAM COUNTER ADC POR - BOD RESET INTERNAL OSCILLATOR CALIB. OSC STACK POINTER WATCHDOG TIMER OSCILLATOR OSCILLATOR CAN CONTROLLER ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER TIMING AND CONTROL BOUNDARYSCAN INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS PROGRAMMING LOGIC INSTRUCTION DECODER INTERRUPT UNIT CONTROL LINES ALU EEPROM STATUS REGISTER USART0 SPI USART1 TWO-WIRE SERIAL INTERFACE ANALOG COMPARATOR DATA REGISTER PORTE DATA DIR. REG. PORTE DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD + - DATA REG. PORTG DATA DIR. REG. PORTG PORTE DRIVERS PORTB DRIVERS PORTD DRIVERS PORTG DRIVERS PE7 - PE0 PB7 - PB0 PD7 - PD0 PG4 - PG0 4 AT90CAN32/64/128 7679HS-CAN-08/08 RESET XTAL1 XTAL2 AT90CAN32/64/128 1.5 Pin Configurations Pinout AT90CAN32/64/128 - TQFP PF5 (ADC5 / TMS) PF4 (ADC4 / TCK) PF6 (ADC6 / TDO) PF7 (ADC7 / TDI) Figure 1-2. PF1 (ADC1) PF0 (ADC0) PF2 (ADC2) PF3 (ADC3) PA0 (AD0) 64 62 51 PA1 (AD1) 50 AVCC AREF GND GND 61 60 55 63 59 58 57 56 54 53 NC (1) 52 49 PA2 (AD2) VCC 1 2 3 4 5 6 7 8 9 48 47 PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2 (ALE) PC7 (A15 / CLKO) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1 (RD) PG0 (WR) (RXD0 / PDI) PE0 (TXD0 / PDO) PE1 (XCK0 / AIN0) PE2 (OC3A / AIN1) PE3 (OC3B / INT4) PE4 (OC3C / INT5) PE5 (T3 / INT6) PE6 (ICP3 / INT7) PE7 INDEX CORNER 46 45 44 43 42 (64-lead TQFP top view) 41 40 39 38 37 36 35 34 33 (SS) PB0 10 (SCK) PB1 11 (MOSI) PB2 12 (MISO) PB3 13 (OC2A) PB4 14 (OC1A) PB5 (OC1B) PB6 15 16 (TXD1 / INT3) PD3 28 (SCL / INT0) PD0 25 (OC0A / OC1C) PB7 17 (TOSC2 ) PG3 18 (TOSC1 ) PG4 19 (ICP1) PD4 29 GND 22 XTAL2 23 RESET 20 XTAL1 24 VCC 21 (TXCAN / XCK1) PD5 30 (RXCAN / T1) PD6 31 (SDA / INT1) PD1 26 (RXD1 / INT2) PD2 27 (T0) PD7 32 (2) (1) (2) NC = Do not connect (May be used in future devices) Timer2 Oscillator (2) 5 7679HS-CAN-08/08 Figure 1-3. Pinout AT90CAN32/64/128 - QFN PF5 (ADC5 / TMS) PF6 (ADC6 / TDO) PF4 (ADC4 / TCK) PF7 (ADC7 / TDI) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PA0 (AD0) PA1 (AD1) 50 59 64 63 62 61 60 58 57 56 55 54 53 52 51 NC (1) 49 PA2 (AD2) AVCC AREF GND GND VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 17 18 19 21 22 23 24 25 26 27 28 29 30 31 32 48 47 PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2 (ALE) PC7 (A15 / CLKO) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1 (RD) PG0 (WR) (RXD0 / PDI) PE0 (TXD0 / PDO) PE1 (XCK0 / AIN0) PE2 (OC3A / AIN1) PE3 (OC3B / INT4) PE4 (OC3C / INT5) PE5 (T3 / INT6) PE6 (ICP3 / INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC2A) PB4 (OC1A) PB5 (OC1B) PB6 INDEX CORNER 46 45 44 43 42 41 (64-lead QFN top view) 40 39 38 37 36 35 34 33 (OC0A / OC1C) PB7 (SDA / INT1) PD1 (TXD1 / INT3) PD3 (SCL / INT0) PD0 (RXD1 / INT2) PD2 (1) (2) NC = Do not connect (May be used in future devices) Timer2 Oscillator Note: The large center pad underneath the QFN package is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. 1.6 1.6.1 Pin Descriptions VCC Digital supply voltage. 1.6.2 GND Ground. 6 AT90CAN32/64/128 7679HS-CAN-08/08 (TXCAN / XCK1) PD5 (RXCAN / T1) PD6 (TOSC2 ) PG3 (TOSC1 ) PG4 (ICP1) PD4 (T0) PD7 RESET XTAL2 (2) (2) XTAL1 GND VCC AT90CAN32/64/128 1.6.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 74. 1.6.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 76. 1.6.5 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the AT90CAN32/64/128 as listed on page 78. 1.6.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 80. 1.6.7 Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 83. 1.6.8 Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. 7 7679HS-CAN-08/08 Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pullup resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. 1.6.9 Port G (PG4..PG0) Port G is a 5-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 88. 1.6.10 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteed to generate a reset. The I/O ports of the AVR are immediately reset to their initial state even if the clock is not running. The clock is needed to reset the rest of the AT90CAN32/64/128. 1.6.11 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 1.6.12 XTAL2 Output from the inverting Oscillator amplifier. 1.6.13 AVCC AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 1.6.14 AREF This is the analog reference pin for the A/D Converter. 2. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 8 AT90CAN32/64/128 7679HS-CAN-08/08 AT90CAN32/64/128 3. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) Name Reserved Reserved Reserved Reserved Reserved CANMSG CANSTMH CANSTML CANIDM1 CANIDM2 CANIDM3 CANIDM4 CANIDT1 CANIDT2 CANIDT3 CANIDT4 CANCDMOB CANSTMOB CANPAGE CANHPMOB CANREC CANTEC CANTTCH CANTTCL CANTIMH CANTIML CANTCON CANBT3 CANBT2 CANBT1 CANSIT1 CANSIT2 CANIE1 CANIE2 CANEN1 CANEN2 CANGIE CANGIT CANGSTA CANGCON Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR1 UBRR1H UBRR1L Reserved UCSR1C UCSR1B UCSR1A Reserved UDR0 UBRR0H UBRR0L Reserved UCSR0C UCSR0B UCSR0A Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page MSG 7 TIMSTM15 TIMSTM7 IDMSK28 IDMSK20 IDMSK12 IDMSK4 IDT28 IDT20 IDT12 IDT4 CONMOB1 DLCW MOBNB3 HPMOB3 REC7 TEC7 TIMTTC15 TIMTTC7 CANTIM15 CANTIM7 TPRSC7 - - - - SIT7 - IEMOB7 - ENMOB7 ENIT CANIT - ABRQ MSG 6 TIMSTM14 TIMSTM6 IDMSK27 IDMSK19 IDMSK11 IDMSK3 IDT27 IDT19 IDT11 IDT3 CONMOB0 TXOK MOBNB2 HPMOB2 REC6 TEC6 TIMTTC14 TIMTTC6 CANTIM14 CANTIM6 TPRSC6 PHS22 SJW1 BRP5 SIT14 SIT6 IEMOB14 IEMOB6 ENMOB14 ENMOB6 ENBOFF BOFFIT OVRG OVRQ MSG 5 TIMSTM13 TIMSTM5 IDMSK26 IDMSK18 IDMSK10 IDMSK2 IDT26 IDT18 IDT10 IDT2 RPLV RXOK MOBNB1 HPMOB1 REC5 TEC5 TIMTTC13 TIMTTC5 CANTIM13 CANTIM5 TPRSC5 PHS21 SJW0 BRP4 SIT13 SIT5 IEMOB13 IEMOB5 ENMOB13 ENMOB5 ENRX OVRTIM - TTC MSG 4 TIMSTM12 TIMSTM4 IDMSK25 IDMSK17 IDMSK9 IDMSK1 IDT25 IDT17 IDT9 IDT1 IDE BERR MOBNB0 HPMOB0 REC4 TEC4 TIMTTC12 TIMTTC4 CANTIM12 CANTIM4 TPRSC4 PHS20 - BRP3 SIT12 SIT4 IEMOB12 IEMOB4 ENMOB12 ENMOB4 ENTX BXOK TXBSY SYNTTC MSG 3 TIMSTM11 TIMSTM3 IDMSK24 IDMSK16 IDMSK8 IDMSK0 IDT24 IDT16 IDT8 IDT0 DLC3 SERR AINC CGP3 REC3 TEC3 TIMTTC11 TIMTTC3 CANTIM11 CANTIM3 TPRSC3 PHS12 PRS2 BRP2 SIT11 SIT3 IEMOB11 IEMOB3 ENMOB11 ENMOB3 ENERR SERG RXBSY LISTEN MSG 2 TIMSTM10 TIMSTM2 IDMSK23 IDMSK15 IDMSK7 RTRMSK IDT23 IDT15 IDT7 RTRTAG DLC2 CERR INDX2 CGP2 REC2 TEC2 TIMTTC10 TIMTTC2 CANTIM10 CANTIM2 TPRSC2 PHS11 PRS1 BRP1 SIT10 SIT2 IEMOB10 IEMOB2 ENMOB10 ENMOB2 ENBX CERG ENFG TEST MSG 1 TIMSTM9 TIMSTM1 IDMSK22 IDMSK14 IDMSK6 - IDT22 IDT14 IDT6 RB1TAG DLC1 FERR INDX1 CGP1 REC1 TEC1 TIMTTC9 TIMTTC1 CANTIM9 CANTIM1 TRPSC1 PHS10 PRS0 BRP0 SIT9 SIT1 IEMOB9 IEMOB1 ENMOB9 ENMOB1 ENERG FERG BOFF ENA/STB MSG 0 TIMSTM8 TIMSTM0 IDMSK21 IDMSK13 IDMSK5 IDEMSK IDT21 IDT13 IDT5 RB0TAG DLC0 AERR INDX0 CGP0 REC0 TEC0 TIMTTC8 TIMTTC0 CANTIM8 CANTIM0 TPRSC0 SMP - - SIT8 SIT0 IEMOB8 IEMOB0 ENMOB8 ENMOB0 ENOVRT AERG ERRP SWRES page 266 page 266 page 266 page 265 page 265 page 265 page 265 page 263 page 263 page 263 page 263 page 262 page 261 page 260 page 260 page 260 page 260 page 260 page 260 page 259 page 259 page 259 page 258 page 258 page 257 page 257 page 257 page 257 page 257 page 256 page 256 page 255 page 254 page 253 page 252 UDR17 - UBRR17 - RXCIE1 RXC1 UDR07 - UBRR07 - RXCIE0 RXC0 UDR16 - UBRR16 UMSEL1 TXCIE1 TXC1 UDR06 - UBRR06 UMSEL0 TXCIE0 TXC0 UDR15 - UBRR15 UPM11 UDRIE1 UDRE1 UDR05 - UBRR05 UPM01 UDRIE0 UDRE0 UDR14 - UBRR14 UPM10 RXEN1 FE1 UDR04 - UBRR04 UPM00 RXEN0 FE0 UDR13 UBRR111 UBRR13 USBS1 TXEN1 DOR1 UDR03 UBRR011 UBRR03 USBS0 TXEN0 DOR0 UDR12 UBRR110 UBRR12 UCSZ11 UCSZ12 UPE1 UDR02 UBRR010 UBRR02 UCSZ01 UCSZ02 UPE0 UDR11 UBRR19 UBRR11 UCSZ10 RXB81 U2X1 UDR01 UBRR09 UBRR01 UCSZ00 RXB80 U2X0 UDR10 UBRR18 UBRR10 UCPOL1 TXB81 MPCM1 UDR00 UBRR08 UBRR00 UCPOL0 TXB80 MPCM0 page 195 page 199 page 199 page 198 page 197 page 195 page 195 page 199 page 199 page 197 page 196 page 195 9 7679HS-CAN-08/08 Address (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) Name Reserved Reserved TWCR TWDR TWAR TWSR TWBR Reserved ASSR Reserved Reserved OCR2A TCNT2 Reserved TCCR2A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR3CH OCR3CL OCR3BH OCR3BL OCR3AH OCR3AL ICR3H ICR3L TCNT3H TCNT3L Reserved TCCR3C TCCR3B TCCR3A Reserved Reserved OCR1CH OCR1CL OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page TWINT TWDR7 TWAR6 TWS7 TWBR7 - TWEA TWDR6 TWAR5 TWS6 TWBR6 - TWSTA TWDR5 TWAR4 TWS5 TWBR5 - TWSTO TWDR4 TWAR3 TWS4 TWBR4 EXCLK TWWC TWDR3 TWAR2 TWS3 TWBR3 AS2 TWEN TWDR2 TWAR1 - TWBR2 TCN2UB - TWDR1 TWAR0 TWPS1 TWBR1 OCR2UB TWIE TWDR0 TWGCE TWPS0 TWBR0 TCR2UB page 212 page 214 page 214 page 213 page 212 page 160 OCR2A7 TCNT27 FOC2A OCR2A6 TCNT26 WGM20 OCR2A5 TCNT25 COM2A1 OCR2A4 TCNT24 COM2A0 OCR2A3 TCNT23 WGM21 OCR2A2 TCNT22 CS22 OCR2A1 TCNT21 CS21 OCR2A0 TCNT20 CS20 page 159 page 159 page 164 OCR3C15 OCR3C7 OCR3B15 OCR3B7 OCR3A15 OCR3A7 ICR315 ICR37 TCNT315 TCNT37 FOC3A ICNC3 COM3A1 OCR3C14 OCR3C6 OCR3B14 OCR3B6 OCR3A14 OCR3A6 ICR314 ICR36 TCNT314 TCNT36 FOC3B ICES3 COM3A0 OCR3C13 OCR3C5 OCR3B13 OCR3B5 OCR3A13 OCR3A5 ICR313 ICR35 TCNT313 TCNT35 FOC3C - COM3B1 OCR3C12 OCR3C4 OCR3B12 OCR3B4 OCR3A12 OCR3A4 ICR312 ICR34 TCNT312 TCNT34 - WGM33 COM3B0 OCR3C11 OCR3C3 OCR3B11 OCR3B3 OCR3A11 OCR3A3 ICR311 ICR33 TCNT311 TCNT33 - WGM32 COM3C1 OCR3C10 OCR3C2 OCR3B10 OCR3B2 OCR3A10 OCR3A2 ICR310 ICR32 TCNT310 TCNT32 - CS32 COM3C0 OCR3C9 OCR3C1 OCR3B9 OCR3B1 OCR3A9 OCR3A1 ICR39 ICR31 TCNT39 TCNT31 - CS31 WGM31 OCR3C8 OCR3C0 OCR3B8 OCR3B0 OCR3A8 OCR3A0 ICR38 ICR30 TCNT38 TCNT30 page 141 page 141 page 141 page 141 page 141 page 141 page 142 page 142 page 140 page 140 page 140 CS30 WGM30 page 138 page 135 OCR1C15 OCR1C7 OCR1B15 OCR1B7 OCR1A15 OCR1A7 ICR115 ICR17 TCNT115 TCNT17 FOC1A ICNC1 COM1A1 - ADC7D OCR1C14 OCR1C6 OCR1B14 OCR1B6 OCR1A14 OCR1A6 ICR114 ICR16 TCNT114 TCNT16 FOC1B ICES1 COM1A0 - ADC6D OCR1C13 OCR1C5 OCR1B13 OCR1B5 OCR1A13 OCR1A5 ICR113 ICR15 TCNT113 TCNT15 FOC1C - COM1B1 - ADC5D OCR1C12 OCR1C4 OCR1B12 OCR1B4 OCR1A12 OCR1A4 ICR112 ICR14 TCNT112 TCNT14 - WGM13 COM1B0 - ADC4D OCR1C11 OCR1C3 OCR1B11 OCR1B3 OCR1A11 OCR1A3 ICR111 ICR13 TCNT111 TCNT13 - WGM12 COM1C1 - ADC3D OCR1C10 OCR1C2 OCR1B10 OCR1B2 OCR1A10 OCR1A2 ICR110 ICR12 TCNT110 TCNT12 - CS12 COM1C0 - ADC2D OCR1C9 OCR1C1 OCR1B9 OCR1B1 OCR1A9 OCR1A1 ICR19 ICR11 TCNT19 TCNT11 - CS11 WGM11 AIN1D ADC1D OCR1C8 OCR1C0 OCR1B8 OCR1B0 OCR1A8 OCR1A0 ICR18 ICR10 TCNT18 TCNT10 - CS10 WGM10 AIN0D ADC0D page 141 page 141 page 141 page 141 page 141 page 141 page 142 page 142 page 140 page 140 page 139 page 138 page 135 page 272 page 292 10 AT90CAN32/64/128 7679HS-CAN-08/08 AT90CAN32/64/128 Address (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) Name ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved XMCRB XMCRA Reserved Reserved TIMSK3 TIMSK2 TIMSK1 TIMSK0 Reserved Reserved Reserved EICRB EICRA Reserved Reserved OSCCAL Reserved Reserved Reserved Reserved CLKPR WDTCR SREG SPH SPL Reserved RAMPZ(1) Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved Reserved OCR0A TCNT0 Reserved TCCR0A GTCCR EEARH(2) EEARL EEDR EECR GPIOR0 EIMSK EIFR Reserved Bit 7 REFS1 - ADEN - / ADC9 ADC7 / ADC1 Bit 6 REFS0 ACME ADSC - / ADC8 ADC6 / ADC0 Bit 5 ADLAR - ADATE - / ADC7 ADC5 / - Bit 4 MUX4 - ADIF - / ADC6 ADC4 / - Bit 3 MUX3 - ADIE - / ADC5 ADC3 / - Bit 2 MUX2 ADTS2 ADPS2 - / ADC4 ADC2 / - Bit 1 MUX1 ADTS1 ADPS1 ADC9 / ADC3 ADC1 / - Bit 0 MUX0 ADTS0 ADPS0 ADC8 / ADC2 ADC0 / Page page 287 page 291, 269 page 289 page 290 page 290 XMBK SRE - SRL2 - SRL1 - SRL0 - SRW11 XMM2 SRW10 XMM1 SRW01 XMM0 SRW00 page 33 page 32 - - - - - - - - ICIE3 - ICIE1 - - - - - OCIE3C - OCIE1C - OCIE3B - OCIE1B - OCIE3A OCIE2A OCIE1A OCIE0A TOIE3 TOIE2 TOIE1 TOIE0 page 142 page 162 page 142 page 112 ISC71 ISC31 ISC70 ISC30 ISC61 ISC21 ISC60 ISC20 ISC51 ISC11 ISC50 ISC10 ISC41 ISC01 ISC40 ISC00 page 94 page 93 - CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 page 42 CLKPCE - I SP15 SP7 - - - T SP14 SP6 - - - H SP13 SP5 - - WDCE S SP12 SP4 - CLKPS3 WDE V SP11 SP3 - CLKPS2 WDP2 N SP10 SP2 - CLKPS1 WDP1 Z SP9 SP1 - CLKPS0 WDP0 C SP8 SP0 RAMPZ0 page 44 page 58 page 11 page 14 page 14 page 13 SPMIE - JTD - - IDRD/OCDR7 ACD SPD7 SPIF SPIE GPIOR27 GPIOR17 RWWSB - - - - OCDR6 ACBG SPD6 WCOL SPE GPIOR26 GPIOR16 - - - - - OCDR5 ACO SPD5 - DORD GPIOR25 GPIOR15 RWWSRE - PUD JTRF - OCDR4 ACI SPD4 - MSTR GPIOR24 GPIOR14 BLBSET - - WDRF SM2 OCDR3 ACIE SPD3 - CPOL GPIOR23 GPIOR13 PGWRT - - BORF SM1 OCDR2 ACIC SPD2 - CPHA GPIOR22 GPIOR12 PGERS - IVSEL EXTRF SM0 OCDR1 ACIS1 SPD1 - SPR1 GPIOR21 GPIOR11 SPMEN - IVCE PORF SE OCDR0 ACIS0 SPD0 SPI2X SPR0 GPIOR20 GPIOR10 page 326 page 64, 73, 304 page 56, 304 page 46 page 299 page 270 page 175 page 175 page 173 page 36 page 36 OCR0A7 TCNT07 FOC0A TSM - EEAR7 EEDR7 - GPIOR07 INT7 INTF7 OCR0A6 TCNT06 WGM00 - - EEAR6 EEDR6 - GPIOR06 INT6 INTF6 OCR0A5 TCNT05 COM0A1 - - EEAR5 EEDR5 - GPIOR05 INT5 INTF5 OCR0A4 TCNT04 COM0A0 - - EEAR4 EEDR4 - GPIOR04 INT4 INTF4 OCR0A3 TCNT03 WGM01 - EEAR11 EEAR3 EEDR3 EERIE GPIOR03 INT3 INTF3 OCR0A2 TCNT02 CS02 - EEAR10 EEAR2 EEDR2 EEMWE GPIOR02 INT2 INTF2 OCR0A1 TCNT01 CS01 PSR2 EEAR9 EEAR1 EEDR1 EEWE GPIOR01 INT1 INTF1 OCR0A0 TCNT00 CS00 PSR310 EEAR8 EEAR0 EEDR0 EERE GPIOR00 INT0 INTF0 page 112 page 111 page 109 page 98, 164 page 22 page 22 page 23 page 23 page 36 page 95 page 95 11 7679HS-CAN-08/08 Address 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name Reserved Reserved TIFR3 TIFR2 TIFR1 TIFR0 PORTG DDRG PING PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page - - - - - - - PORTF7 DDF7 PINF7 PORTE7 DDE7 PINE7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7 - - - - - - - PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6 ICF3 - ICF1 - - - - PORTF5 DDF5 PINF5 PORTE5 DDE5 PINE5 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5 - - - - PORTG4 DDG4 PING4 PORTF4 DDF4 PINF4 PORTE4 DDE4 PINE4 PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4 OCF3C - OCF1C - PORTG3 DDG3 PING3 PORTF3 DDF3 PINF3 PORTE3 DDE3 PINE3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3 OCF3B - OCF1B - PORTG2 DDG2 PING2 PORTF2 DDF2 PINF2 PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 OCF3A OCF2A OCF1A OCF0A PORTG1 DDG1 PING1 PORTF1 DDF1 PINF1 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 TOV3 TOV2 TOV1 TOV0 PORTG0 DDG0 PING0 PORTF0 DDF0 PINF0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 page 143 page 162 page 143 page 112 page 92 page 92 page 92 page 91 page 91 page 92 page 91 page 91 page 91 page 91 page 91 page 91 page 90 page 90 page 90 page 90 page 90 page 90 page 89 page 90 page 90 Notes: 1. Address bits exceeding PCMSB (Table 25-11 on page 341) are don't care. 2. Address bits exceeding EEAMSB (Table 25-12 on page 341) are don't care. 3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 4. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 5. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 6. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90CAN32/64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 12 AT90CAN32/64/128 7679HS-CAN-08/08 AT90CAN32/64/128 4. Ordering Information Ordering Code (1) Speed (MHz) 16 16 16 16 16 16 16 16 16 16 16 16 Power Supply (V) 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 Package A2 64 Z64-1 A2 64 Z64-1 A2 64 Z64-2 A2 64 Z64-2 A2 64 Z64-2 A2 64 Z64-2 Operation Range Industrial (-40 to +85C) Industrial (-40 to +85C) Industrial (-40 to +85C) Green Industrial (-40 to +85C) Green Industrial (-40 to +85C) Industrial (-40 to +85C) Industrial (-40 to +85C) Green Industrial (-40 to +85C) Green Industrial (-40 to +85C) Industrial (-40 to +85C) Industrial (-40 to +85C) Green Industrial (-40 to +85C) Green Product Marking AT90CAN32-16AI AT90CAN32-16MI AT90CAN32-16AU AT90CAN32-16MU AT90CAN64-16AI AT90CAN64-16MI AT90CAN64-16AU AT90CAN64-16MU AT90CAN128-16AI AT90CAN128-16MI AT90CAN128-16AU AT90CAN128-16MU AT90CAN32-16AI AT90CAN32-16MI AT90CAN32-16AU AT90CAN32-16MU AT90CAN64-16AI AT90CAN64-16MI AT90CAN64-16AU AT90CAN64-16MU AT90CAN128-16AI AT90CAN128-16MI AT90CAN128-16AU AT90CAN128-16MU Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 5. Packaging Information Package Type A2 64 Z64-1 Z64-2 64-Lead, Thin (1.0 mm / 0.03937 in) Plastic Gull Wing Quad Flat Package. 64-Lead, QFN, Exposed Die Attach Pad D2/E2: 5.4 0.1mm / 0.212 0.004 in. 64-Lead, QFN, Exposed Die Attach Pad D2/E2: 6.0 0.1mm / 0.236 0.004 in. 13 7679HS-CAN-08/08 5.1 TQFP64 64 PINS THIN QUAD FLAT PACK D 0O to 7O AL 64 e 1 E E1 f J C TOP VIEW 11O / 13O SIDE VIEW A2 DRAWINGS NOT SCALED 0.100 mm LEAD COPLANARITY MM Min A A2 C D D1 E E1 J L e f ---0.95 0.09 Max 1.20 1.05 0.20 Min ---0.037 0.004 INCH Max 0.047 0.041 0.008 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.05 0.45 0.15 0.75 0.630 BSC 0.551 BSC 0.630 BSC 0.551 BSC 0.002 0.018 0.006 0.030 0.80 BSC 0.30 0.45 0.0315 BSC 0.012 0.018 14 AT90CAN32/64/128 7679HS-CAN-08/08 AT90CAN32/64/128 5.2 QFN64 15 7679HS-CAN-08/08 16 AT90CAN32/64/128 7679HS-CAN-08/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2008 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 7679HS-CAN-08/08 |
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